HDL Design for exa hertz clock based 2e31-1 exa bits per second (ebps) prbs design for ultra high speed applications/products

The Design is mainly Intended for High Speed Random Frequency Carrier Wave Generator of Exa Bits Per Second Ebps (Exa Bits Per Second) Data Rate 2e23-1 Tapped PRBS Pattern Sequence. The PRBS is Designed by using LFSR Linear Feed Back Shift Register and XOR Gate with Specific Tapping Points as per CCITT ITU Standards. RTL Design Architecture Implemented by using VHDL and/ Verilog HDL, Programming and Debugging Done by using Spartan III FPGA Kit. Transmission done through this carrier frequency. Propagation Carrier Done either Serially / Parallel lines I/O.